OSM: Off-Chip Shared Memory for GPUs.
- Sina Darabi,
- ,
- Negar Akbarzadeh,
- Hajar Falahati,
- Pejman Lotfi-Kamran,
- Mohammad Sadrosadati
- Sharif University of Technology,
- Institute for Research in Fundamental Sciences
Research Output:
Journal Article or Conference Article in Journal
Journal article
Peer-reviewPublication Information
Output type
Research Output:
Journal Article or Conference Article in Journal
Journal article
Peer-reviewOriginal language
EnglishArticle number
12Pages from-to (Number of pages)
Pages 3415-3429 (15 pages)Journal (Volume, Issue Number)
IEEE Transactions on Parallel and Distributed Systems (Volume 33, Issue 12)Publication milestones
- Published - 24/02/2022
Publication status
Published - 24/02/2022
Publication IDs
- Scopus: 85125700009
Abstract
Graphics Processing Units (GPUs) employ a shared memory, a software-managed cache for programmers, in each streaming multiprocessor to accelerate data sharing among the threads in a thread block. Although 60% of the shared memory space is underutilized, on average, there are some workloads that demand higher shared memory capacities. Therefore, improving shared memory utilization while satisfying the needs of shared memory intensive workloads is challenging. We make a key observation that the lifetime of each shared memory address is significantly shorter than the execution time of a thread block. In this paper, we first propose Off-Chip Shared Memory (OSM) that allocates shared memory space in the off-chip memory, and accelerates accesses to it via a small on-chip cache. Using an 8 KB cache for shared memory addresses, OSM provides almost the same performance as the baseline GPU that uses 96 KB on-chip shared memory. OSM improves GPU performance in two ways. First, it allocates higher shared memory capacities in the off-chip memory, and improves thread-level parallelism (TLP). Second, it designs a unified cache for shared memory and global address spaces, providing more caching space for global memory address space even for the workloads with high shared memory utilization. Our experimental results show an average 21% and 18% IPC improvement compared to the baseline and the state-of-the-art architectures.
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