CXL Memory Performance for In-Memory Data Processing
- Marcel Weisgut,
- Daniel Ritter,
- ,
- Lawrence Benson,
- Tilmann Rabl
Research Output:
Journal Article or Conference Article in Journal
Journal article
Peer-reviewOpen access
Publication Information
Output type
Research Output:
Journal Article or Conference Article in Journal
Journal article
Peer-reviewOriginal language
EnglishPages from-to (Number of pages)
Pages 3119-3133 (15 pages)Journal (Volume, Issue Number)
Proceedings of the VLDB Endowment (Volume 18, Issue 9)Publication milestones
- Published - 01/05/2025
Publication status
Published - 01/05/2025
ISSN
2150-8097Publication IDs
- ORCID: /0000-0001-6838-4854/work/200135837
- Scopus: 105014239867
Abstract
The Compute Express Link (CXL) standard enables new forms of memory management and access across devices and servers. Based on PCIe, it enables cache-coherent access to remote memory. This widens the design space for database systems by expanding the available memory beyond memory local to the CPU. Efficiently utilizing CXL-attached memory requires conscious decisions by data systems about data placement and management. In this paper, we provide an in-depth analysis of database operation performance with data interleaved across multiple CXL memory devices. We experimentally evaluate the memory access performance for basic access patterns, the performance impact of placing data across multiple CXL memory devices for in-memory column scans and in-memory B+tree operations, and the performance impact of placing data in CXL memory for an in-memory database system when running the analytical TPC-H workload. Our experiments show that access to CXL-attached memory does not have to penalize performance over local access, but careful workload-aware data management is required. Our TPC-H evaluation shows that placing table columns based on access frequencies allows storing over 80% of the table data in CXL memory with a performance of 85% of a local-memory-only solution.
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Funding Details
We thank Seagate Technology LLC and Intel Corporation for their support. This work was partially funded by SAP, the German Research Foundation (ref. 414984028), the European Union’s Horizon 2020 research and innovation programme (ref. 957407), and the Independent Research Fund Denmark’s Inge Lehmann program (grant agreement number 0171-00062B).
FundersFunding numbers
DFF
0171-00062B
